Biased and Unbiased HAST Testing
Considered within the semiconductor industry as the fast and effective alternative to Temperature Humidity Bias testing (THB), Highly-Accelerated Temperature and Humidity Stress Test (HAST) is a critical part of the device package Qualification process and is used to evaluate the reliability of non-hermetic packaged devices in humid environments. The test employs severe conditions of temperature and humidity created within a pressure vessel, to accelerate moisture penetration through the external protective plastic package encapsulant or seal.
Today’s low geometry semiconductor devices with higher leakage core current create internal dissipation. The resultant heating as a result of power dissipation tends to drive moisture away from the die and thereby hinders moisture-related failure mechanisms.
As per JEDEC JESD22-A110D, if DUT dissipation exceeds 200mW – Tj should be calculated. If Tj >10°C above chamber ambient then – cycled bias should be applied. Cycled bias allows moisture collection on the die during the off periods. Cycling the DUT bias with a 50% duty cycle is optimal for most plastic encapsulated devcies.
Many devices can be set into a RESET or “Sleep” mode in order to reduce DUT dissipation. This often requires dynamic signals applied to the DUT. These signals are provided by incorporating the use of dynamic driver cards.
- Performed according to JEDEC standard JESD22-A110 (Biased HAST) and JESDA118 (Unbiased HAST)
- Typical Conditions: 130°C/85%RH/33.3 psia and 110°C/85%RH.17.7 psia
- Duration: 96 or 264 hours
- Power cycled Biased HAST testing performed for higher power devices
- Typical lots sizes 3 x 25 units
- Reltech has over 25 years experience in HAST testing and the design and manufacture of Biased HAST DUT boards.
- Application specific PCB manufacturing techniques are employed to withstand the harsh environment
- Careful DUT socket type selection is critical
- Real time System and DUT monitoring and event logging.
- HAST systems available with up to 116 electrical I/0 connections